It is a problem that the performance of large area photodiodes can be influenced by localised defects arising from the growth of their semiconductor materials or from their manufacturing process. This problem affects, but is not limited to, photodiodes in the semiconductor mercury cadmium telluride (MCT), in which damage sites in the semiconductor crystal lattice exhibit electrical conductivity. Consequently any damage site that coincides with the p-n junction of a photodiode creates an electrical leakage path in parallel with the p-n junction that is associated with excess electrical current and noise in operation of the photodiode.
Although damage sites (defects) can be microscopic in size, their influence may have a major detrimental effect on the photodiode performance. This invention describes a method of suppressing the influence of defects while adding a minimum of complexity to the operational parameters of the photodiode.
In conventional imaging arrays, each pixel in a matrix of pixels is connected to a readout circuit that performs time division multiplexing of electrical signals from the pixels and exports the signals via one or more output channels. In imaging arrays formed, for example, in MCT, the matrix of MCT pixels is often attached to the readout circuit by indium bump bonding and the readout circuit is in the form of a silicon chip.
It is also a problem that where infra-red imaging photo detector arrays using CMOS Readout IC (ROIC) technology are configured using a subpixel architecture configured under memory control, the memory is usually volatile which therefore requires programming each time the device is powered and used. Sub pixels are unit diode detector elements that are connected to form larger equivalent detector elements at e.g. pixel or macro pixel level. Memory is used to configure array parameters for example the array size, detection area or acuity or to configure macro pixels or to deselect defective detector elements to improve operability, uniformity or yield, either individually or in combination. The memory connects to transistors that control the operation and/or interconnection the sub pixel detector elements. Writing data to the memory operates the transistors to control the array configuration and operation. Such approaches of the prior art are often used due to the simplicity and robustness of memory technology, availability of a suitable programming interface in the host electronics and to support a through life user programming function to retain flexibility in configuring the sub pixel array.
For detector systems that require a sub pixel architecture but do not require reconfiguration through life, this approach then requires the hosts electronics system to provide a memory programming interface to configure the detector array each time the device is powered up and used. This adds cost, complexity, size weight and power to the host electronics system.
For applications using a conventional Photo Conductor (PC) detector, the use of an alternative silicon ROIC is usually impractical or economic; PC technology usually operates is a two terminal device that provides a compact detector with a very simple user interface. Using a conventional photovoltaic (PV) detector approach invariably uses a silicon substrate to fabricate the detector diode array that also has associated micro circuits to provide control functions for the detector diode array.
The features of a conventional imaging array, a large area photo-diode may be produced. Following the example of MCT, an array of multiple small pixels is indium bump bonded to a silicon circuit that can combine in parallel the signals from an arbitrary set of the whole pixel array by externally configuring the readout chip to select the pixels of interest. Large area diodes are simulated by selecting one or more blocks of contiguous pixels, combining the individual signals within the block together, and exporting the combined signals off the readout chip.
This technology becomes useful and economic for larger arrays where the silicon embodies the widely known ROIC to configure and control a large detector array having a user control and programming interface and usually active circuitry to process detector photo currents into usable signal voltages for each detector element. It will be appreciated that such PV technology is more complex for the end user as it requires programming at each power up and use, has signal processing circuits that dissipate significant electrical power and has a more complex user interface. Devices are physically larger, cost more to design, fabricate, and test and to encapsulate.
In addition, the readout chip can be configured to select all the pixels of the array singly, and to process and output their signals, by which means an assessment of each individual pixel can be made to determine its diode characteristics and its electrical noise, and to classify the pixel as normal or defective. By this means defective pixels can be deselected from the blocks that define a large area diode and the performance of the large area diode can be optimised by selecting only those pixels that make a positive contribution to the overall signal to noise ratio of the large area diode.